1. Field of the Invention
The present invention relates to a memory system, and more particularly to a memory system capable of selectively operating in a differential signaling mode or a single-ended signaling mode, and a signaling method in a memory system.
2. Description of the Related Art
The operating speed of a central processing unit (CPU) is relatively higher, for example, over one gigahertz (GHz), whereas the speed of a memory device is relatively lower, for example, about hundreds of megahertz (MHz). Therefore, a chipset such as a memory controller is used for interfacing between a computer system and the memory device. Data transmission between the computer system and the memory controller is performed at a relatively higher speed, but data transmission between the memory controller and the memory device is performed at a relatively lower speed, that is, the speed of the memory device.
As the speed of a semiconductor memory device is increased, signaling in a multi-slot mode between a memory controller and a memory module in which memory devices are mounted may be limited. Further, single-ended signaling may have a limit due to parasitic inductance that is caused between a motherboard and the memory module.
Signaling in a point-to-point mode instead of the multi-slot mode may be adopted in order to solve the above problems of signaling in the multi-slot mode. Additionally, a bus structure may include a repeater in order to achieve a large-capacity memory module in signaling that uses a point-to-point mode. Further, signaling may be performed in a differential signaling mode through a majority of buses in order to enhance the speed of signaling.
FIG. 1 is a block diagram illustrating a conventional memory system. Referring to FIG. 1, the memory system includes a memory module 10 and a memory controller 20. The memory module 10 includes semiconductor memory devices 11, 12, 13 and 14. Signaling between the memory controller 20 and each of the semiconductor memory devices 11, 12, 13 and 14 is performed through buses 1, 2, 3, 4, 5, 6, 7 and 8. Further, signaling among the semiconductor memory devices 11, 12, 13 and 14 is performed through buses 1, 2, 3, 4, 5, 6, 7 and 8. In the conventional memory system shown in FIG. 1, the signaling is performed through all of the buses 1, 2, 3, 4, 5, 6, 7 and 8 in a differential signaling mode.
Signaling in the differential signaling mode through all of the buses increases the power consumption of the memory system.